The embodiments described below involve the developing and ever-expanding field of computer systems and microprocessors. As these fields advance, considerations of efficiencies bear on all aspects of operation and design. One key example of such considerations is efficiency of re-designing or producing revisions of microprocessors after the initial version(s) has been fabricated on a wide scale. Another key area is device size. Particularly, once a microprocessor is designed, manufactured, and widely disseminated, it is not uncommon for the designer and/or manufacturer to determine that errors occurred in the already-distributed product. Indeed, as microprocessor complexity increases, while the time from design to production decreases, there is an increasingly greater chance of such post-production discovery. In the area of microprocessors, the error may be corrected by constructing a newer part, such as a new "revision" as that term is often used in the industry. However, this approach has many drawbacks. For example the error(s) to be corrected may require an immediate or near-immediate correction, while significant time may be needed to design and manufacture the revision to correct the part. As another example, different errors may be discovered at different times and, if a first revision corrects one error, it may be necessary to revise the part one or more additional times as additional errors are subsequently discovered. Still other problems in the prior art approaches are known in the art.
The techniques used to correct post-manufacture errors often depend on the particular type of error. The inventive embodiments described below are particularly beneficial when used to correct at least two types of these errors, namely, correction of micro-operation codes and correction of microinstruction codes. Both of these types of codes include bit values which control operation of numerous aspects of a microprocessor. Thus, it is clear that the bit values for both the micro-operation codes and the microinstructions are critical to ensure proper operation of the microprocessor. Thus, once a microprocessor is manufactured and distributed, a discovery of one more erroneous values for either or both of the micro-operation codes and the microinstructions must be addressed. In this regard, some prior art systems include architectures which permit correction by replacement, or so-called "patching", of the micro-operation codes and microinstruction codes. Patching operates so that the system, in whatever manner, substitutes a new bit pattern (i.e., either a new micro-operation code or a new microinstruction code) in place of the erroneous one, thereby correcting system operation. However, each of these prior art systems has drawbacks, some of which are discussed below.
The inventive embodiments described below are directed in many respects to either or both of the microprogram memory and the instruction codes it stores or similarly to a decode table memory and the micro-operation codes it stores. The microprogram memory is typically a read only memory and referred to in the art as the microROM or microcode ROM. The microprogram memory is a fundamental unit of the microprocessor which receives a "microaddress" and, in response, outputs a "microinstruction" code. The decode table memory is also typically a read only medium and stores the micro-operation codes for a microprocessor. Particularly, and as known in the microprocessor art, each microprocessor is responsive to an instruction set, that is, a level of instructions to which programs are compiled so as to govern the operation of the microprocessor. During operation, many CISC and RISC microprocessors further decode each instruction of the instruction set into what is referred to herein as micro-operation codes. Typically, therefore, the microprocessor includes some type decode table memory which stores the bit values for the micro-operation code(s) corresponding to a given instruction. Note further that some microprocessors implement only one of either the microROM or the decode table memory, while others implement both, while still others use a combination of the two. In all events, one skilled in the art will appreciate the embodiments set forth below and how each may be adopted to those varying configurations.
The inventive embodiments described involve the correction of microinstruction codes after they have been stored in the microROM and/or correction of the micro-operation codes after they have stored in the decode table memory. The microinstruction and micro-operation codes are both multiple bit signals, and the value of most if not all of those bits is used to control some aspect of the microprocessor. Obviously, therefore, the code bits must be set in the appropriate state (i.e., high or low) to cause the intended effect(s) of the given microinstruction or micro-operation code. However, due to the increased complexity and design cycle of microprocessors, it is common for microprocessor manufacturers or designers to discover that one or more microinstructions, as originally stored in either the microROM or the decode table memory, have improper values. However, because the codes are in a read only storage device, it is likely impossible, difficult, or at least undesirable to physically change those microinstruction or micro-operation codes which require correction. Thus, microinstruction or micro-operation codes stored in this manner are often replaced with substitute codes retrievable from an alternative source; these types of substitute codes are often referred to as "patch" codes in the art. Thus, various techniques have arisen in the prior art to implement patch codes.
One prior art technique for providing patch microinstruction codes implements a dedicated read/write memory in the microprocessor separately and in addition to the microROM which stores the original microinstruction codes. In this instance, the sole function of the read/write memory is to store patch microinstructions. When a microaddress is issued to the microROM, it also is coupled to the read/write memory. If the microaddress corresponds to a microinstruction code which should be corrected, the read/write memory outputs the patch microinstruction code. Thereafter, this patch microinstruction code is used by the microprocessor in lieu of the original microinstruction code output by the microROM. This approach, however, suffers various drawbacks. For example, the size of the additional read/write memory must be estimated at the time the microprocessor is designed and, at that time, the exact amount of instructions to be corrected using patch instructions is unknown. Underestimating the desired amount of patching may render the microprocessor useless. For example, if the additional read/write memory is only 2 kbytes and it is later determined that more than 2 kbytes are needed to store patch microinstruction codes, then this approach either fails its purpose or must be supplemented by yet another approach (e.g., dynamic loading of patch microinstruction codes). Conversely, overestimating the desired amount of patching may be highly inefficient. For example, if the additional read/write memory is too large (i.e., greater than what is needed to store patch microinstructions), it represents wasted complexity and device size with respect to the microprocessor.
As demonstrated below, the inventors of the present embodiments recognize various inefficiencies in the above approach including the potential for either underestimating or overestimating the amount of patch microinstruction or micro-operation codes and associated necessary resources. Therefore, there arises a need to address the drawbacks of current microprocessors, particularly in view of these as well as other inefficiencies.